The present invention relates to a sequential logic circuit device which is used in, for example, a computer BIOS controller.
Logic circuits can be classified into a sequential logic circuit which includes flip-flops or similar storage circuits, and a combinational circuit of logic elements (such as an AND, an OR and an INV) which does not include the above-mentioned storage circuits. The sequential logic circuit is composed of pluralities of flip-flops and logic elements intermingled and interconnected as desired but it can be regarded as being made up of a flip-flop group and a logic element combinational circuit connected thereto.
The internal storage state of the sequential logic circuit (such as a shift register) usually varies with each operation clock, even if input data remains intact. In addition, the number of internal storage states increases with enlargement of the circuit scale. On this account, the generation of a test pattern of a high fault detection ratio for circuit testing use is far more difficult than in the case of testing combinational circuits.
A scan design system has been proposed as a solution to this problem (Ando, H., "Testing VLSI with Random Access Scan," Compcon, Spring 80, Digest of Papers, pp. 50-52, Feb. 1980, for example). According to this conventional system, a problem for testing the sequential operation type logic circuit can be solved as a problem for testing the combinational circuit by additionally providing a scan circuit for setting and observing directly from the outside the internal state of the flip-flop group capable of storing a number of logical operation states. By fabricating, for example, as one IC, sequential logic circuit devices each provided with the scan circuit which permits testing of the sequential logic circuit having primarily intended functions, each circuit device can easily be tested.
FIG. 1 shows an example of the sequential logic circuit in which a logic circuit part 10 having an intended function is added with a scan circuit 20 for testing use, based on the conventional scan design system. This example is cited from the above-mentioned literature. The logic circuit part 10 is shown to be divided into a combinational circuit 12 and a flip-flop group 11 composed of a plurality of flip-flops FC for the sake of convenience. The scan circuit 20 is made up of a write circuit 21 and a specify circuit 22. Based on decoded addresses X and Y obtained by decoding a scan address (AxAy) with an X decoder 21x and a Y decoder 21y, the specify circuit 22 selectively specifies one of flip-flop circuits FC in the flip-flop group 11.
For testing the logic circuit part 10 according to the scan design system, each flip-flop circuit FC has such a construction as shown in FIG. 2, for example. A system clock Csy and a clear signal CL can be provided in common to all of the flip-flop circuits FC. In each flip-flop circuit FC input data di from the combinational circuit 12 is loaded by the system clock Csy into a flip-flop FF via a gate G2 and its output data do is applied to the combinational circuit 12. This construction is to implement the intended function of the logic circuit part 10. In order that the logic circuit part 10 may be tested according to the scan design system, each flip-flop circuit FC includes gates G1 and G3, which are enabled by the decoded addresses X and Y which are provided from the specify circuit 22 for selecting the flip-flop circuit FC. A scan set signal Ss from the write circuit 21 is provided via the gate G1 of the selected flip-flop circuit FC to the flip-flop FF to set it. The output logic state of the flip-flop FF of the selected flip-flop circuit FC can be directly taken out of the logic circuit part 10, as a scan out signal Sout, via the gate G3. In the following description the output logic state of this flip-flop FF will also be referred to as the output logic state of the flip-flop circuit FC.
In the normal operation of the logic circuit part 10 as an ordinary logic circuit the scan circuit 20 is inoperative and the logic circuit part 10 performs the intended logical operation based on a system input data Din and the system clock Csy and provides system output data Dout.
The testing of the logic circuit part 10 starts with initializing the flip-flop FF of every flip-flop circuit FC in the flip-flop group 11 to a "0" by the clear signal CL as shown in FIG. 3. Next, a series of scan addresses (AxAy) for specifying flip-flops FF to be set to a "1" in the period T.sub.1 are sequentially applied to the specify circuit 22 and, at the same time, a scan-in signal Sin and a scan clock Csc are applied to the write circuit 21, by which scan set signals Ss are sequentially provided to the flip-flop circuits FC specified by the scan addresses AxAy. Then, after predetermined flip-flop circuits FC have each been set to a predetermined logic state in the period T.sub.1, predetermined system input data Din is applied to the logic circuit part 10 and, at the same time, one system clock Csy is provided, by which a transition is made in the internal state of the logic circuit part 10. For checking whether or not the internal state after the transition is an expected logic state, a series of scan addresses (AxAy) for specifying the flip-flops FF are sequentially applied to the specify circuit 22 in period T.sub.2 and output logic states of the specified flip-flops FF are sequentially read out as scan-out signals Sout. At this time, the system output data Dout after the state transition is also obtained. Thereafter, the clear signal CL is applied again to all the flip-flop circuits FC to initialize them and then the application of the scan set signal Ss to the flip-flop circuits FC, the transition of the internal state of the logic circuit part 10 by the system clock Csy and the readout of the scan-out signal Sout are repeated in the same manner as described above.
As will be seen from the above, the conventional circuit arrangement calls for inputting the clear signal CL prior to the setting by the scan circuit 20, and consequently, those of the flip-flops FF which have already been set and need not be reset will also be reset by the clear signal CL. Hence, the states of all the flip-flops FF in the flip-flop group 11 must be set again --this inevitably increases the time T.sub.1 for setting the flip-flops FF.